The present invention generally relates to communications systems and, more particularly, to a receiver.
In the ATSC (Advanced Television Systems Committee) standard for digital terrestrial television (DTV) in the United States (e.g., see, United States Advanced Television Systems Committee, “ATSC Digital Television Standard”, Document A/53, Sep. 16, 1995), the modulation system consists of a suppressed carrier vestigial sideband (VSB) modulation with an added small in-phase pilot at the suppressed carrier frequency, 11.3 dB below the average signal power, at the lower VSB signal edge. An illustrative frequency spectrum for an ATSC VSB signal is shown in FIG. 1.
In most communications systems, such as ATSC, the receiver uses “blind” algorithms to perform carrier and timing synchronization with the transmitted waveform, where the algorithms do not use any information about the transmitted symbols. For example, an ATSC receiver utilizes the above-noted small in-phase pilot tone to achieve carrier frequency lock, after which some other blind method, such as the well-known Gardner's algorithm, is used to achieve symbol-timing lock.
Once carrier frequency lock and symbol-timing lock have been achieved, “non-blind” or data-aided methods can be used in an auxiliary capacity to maintain the carrier frequency lock and the symbol-timing lock. Data aided methods rely on (partial) knowledge of the information (symbols, bits) being transmitted.
An example of a prior art data-aided carrier tracking loop (CTL) and symbol timing recovery (STR) loop ATSC receiver architecture is shown in FIG. 2. This portion of the ATSC receiver comprises a multiplier 40, interpolator 45, demodulator 50, equalizer 55, timing phase detector 60, carrier phase detector 65, STR element 75 and CT element 70. Signal 39 is a complex sample stream comprising in-phase (I) and quadrature (Q) components representing a received VSB signal at an intermediate frequency (IF) (provided by other components of the receiver, e.g., a tuner (not shown)). It should be noted that complex signal paths are shown as double lines in the figures. In FIG. 2, the data-aided STR loop (the “inner loop” in FIG. 2) is represented by interpolator 45, demodulator 50, equalizer 55, timing phase detector 60 and STR element 75. Similarly, the data-aided CTL (the “outer loop” in FIG. 2) is represented by multiplier 40, interpolator 45, demodulator 50, equalizer 55, carrier phase detector 65 and CT element 70.
Multiplier 40 receives signal 39 and performs de-rotation of the sample stream by a calculated phase angle. For example, the in-phase and quadrature components of signal 39 are rotated by a phase. The latter is provided by signal 71, which represents particular sine and cosine values provided by CT element 70. CT element 70 comprises, e.g., a loop filter, NCO and a sin/cos table as known in the art. The output signal, 44, from multiplier 40 is applied to interpolator 45, which generates a sequence of time interpolated samples synchronized to the transmitter symbol rate. The symbol timing for interpolator 45 is adjusted by STR element 75 via signal 76. The output of interpolator 45 is applied to demodulator 50, which provides a demodulated signal to equalizer 55. Equalizer 55 provides a training/sliced signal 57 (representing the known information about the received signal, this signal is not equalized) and an equalized signal 56. The latter is also provided to other portions (not shown) of the receiver for recovery of the data conveyed therein. Both the equalized signal 56 and the training/sliced signal 57 are applied to timing phase detector 60 and carrier phase detector 65 for detecting phase differences between these signals to provide driving signals 61 and 66 for the STR loop and the CTL, respectively. Unfortunately, each of the data-aided VSB phase detectors represented by detectors 60 and 65 are sensitive to both carrier phase and symbol-timing phase, which creates undesirable coupling between the CTL and STR loops. In addition, the presence of the equalizer in the STR loop may lead to situations where the equalizer and the STR loop “chase each other” causing a decrease in performance.